SDRAM Controller

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This topic contains 7 replies, has 5 voices, and was last updated by  rom.yaz 3 years ago.

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  • #804

    martinayotte
    Participant

    I’m looking for a SDRAM Controller implementation for the miniSpartan6+.

    I’m a bit surprised that such design is not already shared as OpenSource for this board since it features an SDRAM memory since more than a year thru previous design. (ScarabHardware admin, can you share your original design ?)

    I’ve start looking at http://hamsterworks.co.nz/mediawiki/index.php/Simple_SDRAM_Controller used on Papilio-Pro and Logi-Pi boards, but I didn’t figure out how to make it work on miniSpartan6+.

    Anyone has done such implementation ?

    #805

    Ahmad Abbas
    Participant

    @martinayotte

    I tested the SDRAM with Hamsterwork’s controller and it worked. I will upload the code on github tonight.

    #809

    martinayotte
    Participant

    Hi Ahmad,
    Glad to ear that you got some success ! please describe …
    On my side, maybe I was trying too much by being too conservative : I’v tried Memory_tester implementation which leads to tons of warnings …
    Did you simply used SDRAM_Controller.vhd directly and did your own tests ?
    Ciao !

    #839

    roman3017
    Participant

    It looks like XuLA board have very similar SDRAM and FPGA and have open source SDRAM controller in few of their projects here: http://www.xess.com/projects/.

    #841

    martinayotte
    Participant

    Hi Roman3017,
    Those projects seems a bit old, but who cares if they are working …

    #1956

    asukiaaa
    Participant

    Is there any one who succeeded to use SDRAM on miniSpartan6+?

    The following project also tried to use the SDRAM with a controller written by hamsterworks but did not success.
    https://github.com/roman3017/miniSpartan6-plus/tree/master/projects
    https://github.com/roman3017/miniSpartan6-plus/tree/master/projects/ov7670_fr

    Is there any problem on circuit?

    Thanks.

    #2027

    roman3017
    Participant
    #2028

    rom.yaz
    Participant

    hi. i haven’t found any notice anywhere about using MIG with scarab board. wonder why is that?

    our SPARTAN chip should have at least 2(4?) dedicated memory control blocks which can be enabled with MIG.
    but here is the pinout of the chip (page 279):
    http://www.xilinx.com/support/documentation/user_guides/ug385.pdf
    and here is the constraint portion for the SDRAM:

    # SDRAM
    NET "UDQM"    LOC="F15"   | IOSTANDARD=LVTTL;
    NET "SDRAM-CLK" LOC="G16" | IOSTANDARD=LVTTL;
    NET "CKE"     LOC="H16"   | IOSTANDARD=LVTTL;
    NET "BS1"     LOC="T14"   | IOSTANDARD=LVTTL;
    NET "BS0"     LOC="R14"   | IOSTANDARD=LVTTL;
    NET "SDRAM-CSn" LOC="R1"  | IOSTANDARD=LVTTL;
    NET "RASn"    LOC="R2"    | IOSTANDARD=LVTTL;
    NET "CASn"    LOC="T4"    | IOSTANDARD=LVTTL;
    NET "WEn"     LOC="R5"    | IOSTANDARD=LVTTL;
    NET "LDQM"    LOC="T5"    | IOSTANDARD=LVTTL;
    NET "A<0>"    LOC="T15"   | IOSTANDARD=LVTTL;
    NET "A<1>"    LOC="R16"   | IOSTANDARD=LVTTL;
    NET "A<2>"    LOC="P15"   | IOSTANDARD=LVTTL;
    NET "A<3>"    LOC="P16"   | IOSTANDARD=LVTTL;
    NET "A<4>"    LOC="N16"   | IOSTANDARD=LVTTL;
    NET "A<5>"    LOC="M15"   | IOSTANDARD=LVTTL;
    NET "A<6>"    LOC="M16"   | IOSTANDARD=LVTTL;
    NET "A<7>"    LOC="L16"   | IOSTANDARD=LVTTL;
    NET "A<8>"    LOC="K15"   | IOSTANDARD=LVTTL;
    NET "A<9>"    LOC="K16"   | IOSTANDARD=LVTTL;
    NET "A<10>"   LOC="R15"   | IOSTANDARD=LVTTL;
    NET "A<11>"   LOC="J16"   | IOSTANDARD=LVTTL;
    NET "A<12>"   LOC="H15"   | IOSTANDARD=LVTTL;
    NET "D<0>"    LOC="T13"   | IOSTANDARD=LVTTL;
    NET "D<1>"    LOC="T12"   | IOSTANDARD=LVTTL;
    NET "D<2>"    LOC="R12"   | IOSTANDARD=LVTTL;
    NET "D<3>"    LOC="T9"    | IOSTANDARD=LVTTL;
    NET "D<4>"    LOC="R9"    | IOSTANDARD=LVTTL;
    NET "D<5>"    LOC="T7"    | IOSTANDARD=LVTTL;
    NET "D<6>"    LOC="R7"    | IOSTANDARD=LVTTL;
    NET "D<7>"    LOC="T6"    | IOSTANDARD=LVTTL;
    NET "D<8>"    LOC="F16"   | IOSTANDARD=LVTTL;
    NET "D<9>"    LOC="E15"   | IOSTANDARD=LVTTL;
    NET "D<10>"   LOC="E16"   | IOSTANDARD=LVTTL;
    NET "D<11>"   LOC="D16"   | IOSTANDARD=LVTTL;
    NET "D<12>"   LOC="B16"   | IOSTANDARD=LVTTL;
    NET "D<13>"   LOC="B15"   | IOSTANDARD=LVTTL;
    NET "D<14>"   LOC="C16"   | IOSTANDARD=LVTTL;
    NET "D<15>"   LOC="C15"   | IOSTANDARD=LVTTL;

    the memory uses pins spread throughout the SPARTAN chip, and not confined to a particular sector.
    seems the memory was connected to the chip such that the controller cannot be used…

    am i wrong? this is my first FPGA board. can anyone comment on this? THANKS!

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